The present invention relates to a semiconductor device and a method of forming the same, more particularly, to a semiconductor device including a vertical type gate and a method of forming the same.
Recently, 40 nm memory devices are required to be further scaled down. A planner or a recessed gate transistor employing 8F2 (F: minimum feature size) or 6F2 type as a unit cell size is very difficult to be scaled down under 40 nm. A DRAM device employing a 4F2 unit cell can improve the integration density 1.5˜2 times compared to 8F2 or 6F2 unit cell size. Accordingly, the vertical channel transistor is suggested to embody a 4F2 unit cell.
The vertical channel transistor is a transistor in which the channel is orthogonally formed in respect to a surface of a substrate, rather than in parallel thereto. Accordingly, it is not restricted by the channel length although the area of transistor is reduced.
In a vertical channel transistor, a gate electrode is formed around an active pillar which is orthogonally extending from a semiconductor substrate, and source/drain areas are formed at an upper portion and a lower portion of the active pillar so that a channel is orthogonally formed with respect to the surface of the semiconductor substrate. Accordingly, the channel can have a relatively large length although a unit cell size of a transistor is reduced.